1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit memories and, more particularly, to non-volatile random access memory (NVRAM) structures and methods for their manufacture.
2. Description of the Prior Art
Semiconductor memory structures are well-known and designs thereof have been integrated at high densities, providing, at the present state of the art, several million dynamic memory cells or tens of thousands of static memory cells on a single chip along with addressing, sensing and driving circuits allowing data stored therein to be changed at will. Such memories and the speed of access they allow are indispensable to support the high speed of digital processors presently available. However, the maintenance of storage states of the cells requires at least constant application of at least stand-by power and, for dynamic memory cells, periodic refreshing. Since storage states are not otherwise maintained, such memories are referred to as being volatile.
So-called read only memories (ROMS) are not volatile but the contents thereof cannot be changed. ROMs are, nevertheless, useful for personalization of electronic devices and storage of basic operational programming of processors since they generally support very high speed access. Otherwise, other storage media such as magnetic disks, bubble memories and the like have generally been used for non-volatile storage of data when the capability of changing the data must be provided even though access to the data is generally much slower.
To partially overcome the slower access time of other storage devices and media, various caching schemes have been developed which are, in general, quite effective to support the function of available high speed processors. Nevertheless, delays may be encountered when data required by the processor is not present in the cache. Further, use of a cache does not provide freedom from other characteristics of the storage medium utilized such as the mechanical vulnerability of magnetic disk drives to impact, vibration and the like or the need to expand cache capacity, which, itself, requires a degree of processing overhead, to avoid significant delays due to the number of cache misses which may be encountered and the time required to access the desired amount of information from main storage, particularly as compared with processor cycle time.
Non-volatile semiconductor structures are known and have been referred to as programmable read only memories (PROMs) in view of the fact that data can be electrically written or otherwise programmed therein rather than being established in the course of fabrication of the device, as in ROMs. More recently, designs of PROMs have allowed data to be changed by erasure (e.g. by irradiation) and rewriting and are known as erasable programmable read only memories (EPROMS) or, if the erasure is done electrically, electrically erasable programmable read only memories (EEPROMS). These latter structures generally employ electron tunneling phenomena through a thin dielectric layer. Each tunneling operation, however, causes a finite amount of damage to the dielectric and the number of write and erase cycles before failure has been limited. Accordingly, these devices continue to be applied and referred to as various forms of read only memories (i.e. EEPROMs or flash EEPROMs if all cells of a partition of the memory are simultaneously erased) since they are intended for applications in which data will be changed only rarely.
More specifically, memory cells of EEPROMs generally include a structure similar to that of a field effect transistor but have an insulated floating gate electrode to which a control gate is capacitively coupled. Thus, a small voltage on the control gate together with presence or absence of charge stored on the floating gate can allow the reading of the cell while larger voltages on the control gate cause tunneling of electrons from the conduction channel to or from the floating gate for writing or erasure of the EEPROM cell.
Very recently, some electron tunneling mechanisms have been exploited in which the damage to the dielectric during write and/or erase operations is very much reduced. Together with improvements in dielectric quality and distribution of such operations over the memory array, the number of write and erase operations which can be accomplished before device failure has become sufficient to the anticipated service lifetime of computers in which such memories may be employed. Thus such devices can be used much in the manner of random access memories and have thus come to be referred to as non-volatile random access memories (NVRAMs). The number of NVRAM storage cells which may be provided on a single chip has also become comparable to that of at least static RAMs and has begun to approach that of dynamic RAMs.
Tunneling effects on which NVRAMs continue to rely for write and erase operations, however, requires a higher voltage than is required for read operations while high integration density requires small sizes of the memory cells and has led to reduction of logic level voltages used for read operations and other logic functions which may be included on the chip. To avoid breakdown, latch-up and other known types of malfunctions when the higher voltages are applied, isolation structures are generally required between NVRAM cells and write and erase voltages are kept as low as possible to ensure correct operation.
To provide adequate isolation structures in as small an area as possible so-called recessed oxide (ROX) and shallow trench isolation (STI) structures which extend into the substrate and often above the surface of the substrate are generally employed. The floating gate and control gate structures are generally formed to extend along the surface of the isolation structures to provide sufficient coupling ratio of the floating gate and control gate capacitances for reliable operation at a minimized high voltage. Formation of such structures generally requires substantially different processes from those required to form other switching elements having a lower voltage (e.g. limited to approximately the logic-level voltage swing) applied thereto for address decoders, logic, transmission gates, logic voltage level shifters and the like or even complete general purpose processors or special purpose macros on the same chip, generally in a complementary metaloxide-semiconductor (CMOS) technology currently preferred.
More importantly to the manufacturing process at high integration densities, transistors in CMOS and other technologies cannot be formed at minimum size and proximity consistent with tolerating the high voltages required for write and erase operations of EEPROM/NVRAM cells. While many high voltage transistor structures, including CMOS technologies, are known, electrical and structural requirements differ greatly in dependence on the voltage at which they must operate.
For example, in low voltage CMOS (complementary metal-oxide-semiconductor) devices generally used for logic, one transistor of each complementary pair of transistors is formed in an impurity well in a doped substrate or layer of a conductivity type opposite that of the well and a reference, bias or control voltage is applied to the substrate and well to improve off-current and other electrical characteristics of the device. When larger voltages are applied to electrodes of either transistor of a complementary pair of CMOS high voltage driver transistors formed on the same substrate or well, even if dimensioned to withstand the larger voltage, breakdown of the source or drain junctions to the substrate or impurity well, breakdown of the gate oxide, breakdown of the impurity well to the substrate and latch-up can occur unless prevented by other structures which heretofore have involved numerous and/or costly process steps and which may possibly reduce performance. For instance, a thicker epitaxial layer below the high voltage impurity well may affect performance (e.g. aggravate latch-up) of low voltage CMOS devices if not the high voltage devices. The area required for the larger high voltage devices is also a limiting factor in the degree of integration density which can be achieved.
Thin film field effect transistors (TFTs) are also known and familiar to those skilled in the art. Such transistors differ somewhat in structure from transistors formed in accordance with CMOS technology and have relatively lower current drive capability than CMOS transistors of comparable dimensions. Generally, such transistors are formed on an insulative substrate and no reference, bias or control voltage is applied to any structure below the conduction channel which is formed in a doped conductive layer deposited over an insulator. Further, the formation of junctions, doping profiles and gate oxide thicknesses of TFT devices may be specifically designed to withstand and optimally function at the required higher voltages and thus may be very much at variance with the structures which must be formed for lower voltage CMOS logic transistors.